A semiconductor memory such as an SRAM (static random access memory) or ROM (read only memory), having a dummy memory cell and reading the data of a memory cell based on the timing signal of the dummy memory cell, is known.
FIG. 11 is a functional block diagram of a semiconductor memory device provided with a general dummy memory cell. FIGS. 12A to 12G are timing charts of the semiconductor memory device shown in FIG. 11. A simple explanation will be given on a read operation of a SRAM, ROM, or other semiconductor memory device provided with a general dummy memory cell DMC with reference to FIG. 11 and FIGS. 12A to 12G.
A signal S182b is output to a predecoder 16 by an internal timing control circuit 18b. When a predetermined word line WL is activated as shown in FIG. 12C by the predecoder 16 and a word line driver 13b, bit lines BL and xBL (xBL indicates an inverted BL), connected to a memory cell MC, as shown in FIG. 12E, and dummy bit lines DBL and xDBL, connected to a dummy memory cell DMC, as shown in FIG. 12D, are discharged.
A comparator unit 14 compares potentials of the dummy bit lines DBL and xDBL, as shown in FIG. 12D. When, for example, a voltage difference is a previously set threshold voltage Vthcomp or less, it outputs a signal S14 as the timing signal via a timing signal line TL to the internal timing control circuit 18b. 
This timing signal line TL is formed longer than one side length of one row of memory cells 11 from the comparator unit 14 to the internal timing control circuit 18b via a sense amplifier 19 etc. when components are arranged, as shown in, for example, FIG. 14.
The internal timing control circuit 18b outputs a pulse signal S181b based on the signal S14 input via the timing signal line TL, as shown in FIG. 12F, makes the sense amplifier 19 read out the data of the predetermined memory cell MC via the bit lines BL and xBL, as shown in FIG. 12G, and then outputs the signal S182b to make the predecoder 16 and the word line driver 13b deactivate the word line WL, as shown in FIG. 12C, and outputs a signal S183b to make a precharge circuit 15b precharge the predetermined bit lines BL and xBL and dummy bit lines DBL and xDBL to the predetermined potential, as shown in FIGS. 12D and 12E.
In the above reading method, however, after the internal timing control circuit 18b receives the timing signal S14 via the timing signal line TL, the dummy bit lines DBL and xDBL, connected to the dummy memory cell DMC, are precharged; therefore, a start time of the precharge is delayed, so there is a problem of a long cycle time.
Further, the deactivation of the word line WL of the memory cell MC is slow. Therefore, the bit lines BL and xBL of the memory cell MC repeat a precharge and discharge operation in each cycle from a (voltage) power source Vcc to a reference voltage GND, so there is a problem that excessive power is consumed.
Japanese National Publication (Kohyo) No. 2001-521262 discloses a memory circuit in which a dummy memory cell for approximating an RC (resistor-capacitor) delay of a core cell is connected to a word line folded so that a terminal end is provided at a position close to the word line driver in order to shorten the cycle time of the memory.
Further, Japanese National Publication (Kohyo) No. 2001-521262 discloses a memory system in which overlapped columns and a padding column are formed adjacent to the memory cells.
For example, in the memory circuit disclosed in Japanese National Publication (Kohyo) No. 2001-521262, the dummy memory cell is connected to the word line folded so that the terminal end is provided at a position close to the word line driver, a standard delay time is set by a delay time of the RC along with the word line connected to the dummy memory cell, and the read processing is carried out based on the standard delay time, but the precharge etc. of the dummy bit line connected to the dummy memory cell are not controlled and the cycle time due to the precharge is not improved.
For example, in the memory system shown in Japanese Unexamined Patent Publication No. 2001-351385, the “ON” state of the sense amplifier is controlled based on the timing signal (also referred to as a self count control signal) by the overlapped columns and padding column, and the self count control signal is input from the overlapped columns and padding column to the predecoder via a long distance signal line. This signal line is long, therefore the resistance of the signal line becomes large. At the same time, a stray capacitance generated between an interconnect and an inter-layer film is large. Therefore, the time constant of the CR generated by this becomes large. As a result, the transmission characteristics of the signal, particularly the rise and fall (time) of the pulse waveform become slow. This will exert an influence upon the signal transmission. Namely, a delay occurs due to the distance of the signal line, so there is a problem of a long cycle time.